我写的代码:
module en(incode,outcode,s,gs,es);
input[7:0]incode,s;
output[2:0]outcode,gs,es;
reg[2:0]outcode;
wire[7:0]incode;
wire s,gs,es;
wire[8:0]a;
wire[4:0]mc; //输入输出端口定义
assign a={s,incode};
assign mc={outcode,gs,es}; //输入输出端口的位拼接
always@(incode)
begin //outase语句
case(a)
9'b1XXXXXXXX: mc=5'b11111;
9'b011111111: mc=5'b11101;
9'b0XXXXXXX0: mc=5'b00010;
9'b0XXXXXX01: mc=5'b00110;
9'b0XXXXX011: mc=5'b01010;
9'b0XXXX0111: mc=5'b01110;
9'b0XXX01111: mc=5'b10010;
9'b0XX011111: mc=5'b10110;
9'b0X0111111: mc=5'b11010;
9'b001111111: mc=5'b11110;
endcase
end
endmodule
错了,一共10个err,都是这样的:
Error (10137): Verilog HDL Procedural Assignment error at en.v(22): object "mc" on left-hand side of assignment must have a variable data type
对了再追加100