求vhdl写的38译码器代码。

新学，给个例子。

推荐答案推荐于2017-09-19

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity trans38 is
port(
A:in std_logic_vector(2 downto 0);
EN:in std_logic;
Y:out std_logic_vector(7 downto 0)
);
end trans38;

architecture dec_behave of trans38 is
signal sel:std_logic_vector(3 downto 0);
begin
sel<=A&EN;

with sel select
Y<= "00000001" when "0001",
"00000010" when "0011",
"00000100" when "0101",
"00001000" when "0111",
"00010000" when "1001",
"00100000" when "1011",
"01000000" when "1101",
"10000000" when "1111",
"XXXXXXXX" when others;
end dec_behave;

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其他回答

第1个回答 2009-08-09

给你译码部分的代码，其它的自己完成吧：
case data_input(3 downto 0) is
when "0000"=>
seg_data<="11000000"; --0
when "0001"=>
seg_data<="01111001"; --1
when "0010"=>
seg_data<="10100100"; --2
when "0011"=>
seg_data<="00110000"; --3
when "0100"=>
seg_data<="10011001"; --4
when "0101"=>
seg_data<="00010010"; --5
when "0110"=>
seg_data<="10000010"; --6
when "0111"=>
seg_data<="01111000"; --7
when "1000"=>
seg_data<="10000000"; --8
when "1001"=>
seg_data<="00010000"; --9
when "1010"=>
seg_data<="10001000"; --A
when "1011"=>
seg_data<="00000011"; --b
when "1100"=>
seg_data<="11000110"; --c
when "1101"=>
seg_data<="00100001"; --d
when "1110"=>
seg_data<="10000110"; --E
when "1111"=>
seg_data<="00001110"; --F
when others=>
null;
end case;

第2个回答 2019-07-24

给你译码部分的代码，其它的自己完成吧：
case
data_input(3
downto
0)
is
when
"0000"=>
seg_data<="11000000";
--0
when
"0001"=>
seg_data<="01111001";
--1
when
"0010"=>
seg_data<="10100100";
--2
when
"0011"=>
seg_data<="00110000";
--3
when
"0100"=>
seg_data<="10011001";
--4
when
"0101"=>
seg_data<="00010010";
--5
when
"0110"=>
seg_data<="10000010";
--6
when
"0111"=>
seg_data<="01111000";
--7
when
"1000"=>
seg_data<="10000000";
--8
when
"1001"=>
seg_data<="00010000";
--9
when
"1010"=>
seg_data<="10001000";
--A
when
"1011"=>
seg_data<="00000011";
--b
when
"1100"=>
seg_data<="11000110";
--c
when
"1101"=>
seg_data<="00100001";
--d
when
"1110"=>
seg_data<="10000110";
--E
when
"1111"=>
seg_data<="00001110";
--F
when
others=>
null;
end
case;

第3个回答 2020-03-05

ENTITY SN74138 IS
PORT(A,B,C,EN: IN BIT;
Y: OUT BIT_VECTOR(7 DOWNTO 0));
END ENTITY SN74138;
ARCHITECTURE DEMO OF SN74138 IS
SIGNAL ADR:BIT_VECTOR(2 DOWNTO 0);
BEGIN
ADR<=C & B & A;
PROCESS(ADR,EN)
BEGIN
IF EN='0' THEN
Y<=(OTHERS=>'1');
ELSE
CASE ADR IS
WHEN "000" =>Y <="11111110";
WHEN "001" =>Y <="11111101";
WHEN "010" =>Y <="11111011";
WHEN "011" =>Y <="11110111";
WHEN "100" =>Y <="11101111";
WHEN "101" =>Y <="11011111";
WHEN "110" =>Y <="10111111";
WHEN "111" =>Y <="01111111";
END CASE ;
END IF;
END PROCESS;
END ARCHITECTURE DEMO;

第4个回答 2019-12-12

ENTITY
SN74138
IS
PORT(A,B,C,EN:
IN
BIT;
Y:
OUT
BIT_VECTOR(7
DOWNTO
0));
END
ENTITY
SN74138;
ARCHITECTURE
DEMO
OF
SN74138
IS
SIGNAL
ADR:BIT_VECTOR(2
DOWNTO
0);
BEGIN
ADR<=C
&
B
&
A;
PROCESS(ADR,EN)
BEGIN
IF
EN='0'
THEN
Y<=(OTHERS=>'1');
ELSE
CASE
ADR
IS
WHEN
"000"
=>Y
<="11111110";
WHEN
"001"
=>Y
<="11111101";
WHEN
"010"
=>Y
<="11111011";
WHEN
"011"
=>Y
<="11110111";
WHEN
"100"
=>Y
<="11101111";
WHEN
"101"
=>Y
<="11011111";
WHEN
"110"
=>Y
<="10111111";
WHEN
"111"
=>Y
<="01111111";
END
CASE
;
END
IF;
END
PROCESS;
END
ARCHITECTURE
DEMO;

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