用verilog设计一个4位4输入最大数值检测电路。拜托大神帮下忙_百度知...答:module Maximum_value_detection(baimostlarge,a,b,c,d);output[3:0]Mostlarge;input[3:0] a b,c,d;wire[3:0]sum1,sum2,sum3;assign sum1=(a>daob)?a:b;assign sum2=(c>d)?c:d;assign Mostlarge=(sum1>sum2)?sum1:sum2;endmodule module (clk,rstn,n1,n2,n3,n4,m...